using chip master planning in automatic asic design flow to improve performance and buffer resource management

modern integrated circuits consist of millions of standard cells and routing paths. in nano-scale designs, mis-prediction is a dominant problem that may diminish the quality of physical design algorithms or even result in the disruption of the convergence of the design cycle. in this paper, a new planning methodology is presented in which a master-plan of the chip is constructed at the early levels of the physical design, preparing for the operation of the subsequent physical design stages. as a proof of concept study, the proposed planning design flow is applied to both wire planning and buffer resource planning, and the outcomes are compared against conventional contributions. experimental results reveal considerable improvements in terms of performance, timing yield and buffer usage.